This invention relates to a process and system for making a cobalt silicide material suitable for a semiconductor manufacturing process.
Deep submicron (DSM) complementary metal oxide semiconductor (CMOS) circuits make extensive use of interconnects and contacts, and these latter features must be scaleable as well to ensure smooth migrations to smaller geometries. Connections to and between active CMOS FET devices are typically created with so-called xe2x80x9csilicidexe2x80x9d contacts, in which a portion of a source/drain region is converted during a thermal treatment into a metallic low resistance region. Silicidation reactions are well-known, and state of the art manufacturing processes in the 0.18 micron realm typically utilize some form of TiSi2 material as a gate and active region contact. However TiSi2 has several limitations, including linewidth-dependent sheet resistance, low thermal stability, and the fact that titanium can consume an unpredictable amount of silicon during the salicidation reaction. Such characteristics severely handicap the potential for TiSi2 in next generation technologies.
Cobalt silicide (CoSi2) has recently been advocated as a replacement for TiSi2.
One example of a prior art technique disclosing the making and use of CoSi2 is Goto et. al. xe2x80x9cOptimization of Salicide Process for sub 0.1 um CMOS Devicesxe2x80x9d 1994 Symposium on VLSI Technology Digest of Technical Papers, page 119. Cobalt, however, is not without its limitations and problems as well. For instance, Cobalt is sensitive to oxygen and water. Even using very high purity inert gas for the heat treatment, the resulting cobalt salicide is often oxygen contaminated and a sheet resistance of the cobalt salicide thus increases. To prevent such oxidization of the cobalt layer, Goto discloses a cobalt salicide process using a Ti or TiN cap layer on top of the cobalt layer. Thus, a cobalt layer is deposited on a wafer having a top surface comprised of a mixture of exposed surfaces, including dielectric (typically sidewall and isolation) surfaces and silicon surfaces (typically gate and source/drain regions). A Ti or TiN cap layer is deposited on the cobalt layer without exposing the cobalt layer to air. The wafer is then subjected to a first anneal. During the first anneal cobalt reacts with silicon at the surface of the wafer where silicon contacts with cobalt. After the first anneal the wafer is etched in a NH4OH, H2O2, H2O solution and then with a HCl, H2O2, H2O solution. This two-step wet process etches away any metals which are not silicided, that is, Co, Ti, TiN and mixtures thereof. The wafer is then subjected to a second annealing process. In this process conventional semiconductor process quality N2 can be used during the first annealing. After this first anneal the Ti or TiN cap prevents residual oxygen from reacting with Co; therefore the resistance of the produced cobalt salicide does not increase due to an oxygen contamination problem.
As mentioned earlier, to prevent oxidation during silicidation, Ti and TiN are most widely used for capping a Co layer in the Co salicide process. The two materials have different strengths and weaknesses in this regard. For instance, TiN is more stable and does not react much with the Co layer. Nonetheless, Ti is more favored at this time, in large part because Ti is more reactive toward oxygen, and therefore is a potentially a better cap for preventing oxidation of Co. A Ti cap is also known to produce a more thermally stable Co salicide film. This fact is disclosed in Sohn et al. xe2x80x9cEffects of Ti-capping on formation and stability of Co silicidexe2x80x9d Journal of The Electrochemical Society 147 (1) page 373-380, 2000.
The use of Ti capping on Co however results in a complicated silicidation reaction. As Sohn points out, during the first anneal, Si reacts with Co to form a CoSix layer, consisting of primarily CoSi and CoSi2; Ti diffuses into the Co layer as Co reacts with Si; the Co and Ti form a layer of intermetallic mixture and the Ti layer experiences some nitridation. All these reactions take place in the same time causing complex process control consequences. This phenomenon is illustrated generally in FIG. 14.
In addition, for a Ti capped Cobalt silicide process, the first anneal temperature typically needs to be higher than for a comparable TiN capped process. This is a result of the effect of Ti diffusion into the Co layer and the resulting mediation of the silicidation reaction by Ti. In other words, in a Ti-mediated cobalt silicidation process, the presence of Ti retards the Coxe2x80x94Si reaction so that higher anneal temperatures are needed to complete the total reaction. According to Sohn, Ti diffuses into the Si interface and silicide grain boundary, thus stabilizing the final CoSi2 film,. Not all deposited Co reacts to form silicide because some Co reacts with the Ti and is converted into a Coxe2x80x94Ti intermetallic mixture layer. Usually in conventional processes, a Ti cap of 1 to 2 times the thickness of Co is used. Using such a large amount of Ti in turn affects the amount of Co that can ultimately react with silicon. All of these effects are hard to predict and control, and this makes the task of process engineering with cobalt silicide quite complicated. For instance, the final thickness of Cobalt silicide needs to be precisely controlled for more advanced generation of process because of the scaling down of source and drain junction depth.
Thus, although the conventional Co salicide process generally meets the requirement of advanced process of less than 0.1 um feature size, there is need to further improve the Co salicide process, and to ensure that it will be useable even below such feature size. There is a substantial need in the industry to have an extremely small feature size/line width Co silicide process that achieves such scaled down thicknesses yet has good thermal stability to withstand anneal temperature near 800 to 900 degrees centigrade without agglomeration. Furthermore, there is a need to be able to control the process with a better process margin, especially as pertains to the thickness and the sheet resistance of the Co silicide film. Finally, there is an additional pressing need for a basic process flow and process tool for forming Co salicide that achieves a higher productivity in conventional semiconductor manufacturing.
A primary object of the present invention therefore is to provide a solution to many of the aforementioned problems associated with the manufacturing of cobalt silicide.
A related object is to provide a high performance, easily manufacturable contact material suitable for a variety of semiconductor applications, including in self-aligned silicide (SALICIDE) applications;
Another object of the present invention is to provide an improved integrated deposition system that is capable of depositing and treating various semiconductor layers, including high performance silicides such as cobalt silicide;
Yet another object of the present invention is to provide cost effective, reliable Co silicide processes suitable for mass implementation of next generation IC technologies in conventional semiconductor fabrication facilities.
A first aspect of the invention therefore concerns a method of forming silicide materials on a silicon based substrate in which a combination of Co an Coxe2x80x94Ti is used. This includes generally the steps of: depositing a first metal layer on the silicon based substrate, the first metal layer including Cobalt (Co); and depositing a second metal layer on at least selected portions of the first metal layer, the second metal layer including an alloy of Cobalt and a refractory metal; and performing a first heat treatment so as to convert at least part of the first metal layer and the silicon based substrate into a first silicide composition having one or more cobalt silicide phases, the one or more cobalt silicide phases being characterized by a first resistitivity; and performing a second heat treatment so as to convert the first composition, including the one or more cobalt silicide phases, into a second silicide composition containing primarily a lower resistivity cobalt silicide phase, the lower resistivity cobalt silicide phase having a resistivity substantially less than the first resistivity.
In a preferred approach for this aspect of the invention, the alloy is a composition including 20 to 80 percent atomic Titanium. In addition, a further step of removing any non-suicides after step (c) is also performed in most instances. Further in a preferred approach, an additional step of: cleaning the silicon substrate so as to substantially remove any non-native oxides is done prior to step (a). In addition, the alloy is preferably a ternary composition of Cobalt, Titanium, and one additional refractory metal and/or carbon.
Further in a preferred approach of this aspect of the invention, steps (a) through (c) are performed in a single semiconductor wafer processing cluster tool, and without exposing a wafer to ambient between such steps. This further increases reliability, productivity and throughput.
Another aspect of the invention concerns forming Co based silicide materials on a silicon based substrate within a cluster tool, and comprising the steps of: depositing a first metal layer on at least selected portions of the silicon based substrate within a first processing chamber of a semiconductor process cluster tool, the first metal layer including an alloy of Cobalt and a refractory metal (preferably Ti). The alloy includes a percentage of refractory metal in the range of 1 to approximately 10 percent. A first heat treatment is performed within the semiconductor process cluster tool so as to convert at least part of the first metal layer and the silicon based substrate into a first silicide composition having one or more cobalt silicide phases, the one or more cobalt silicide phases being characterized by a first resistitivity. After this, a purge treatment within the semiconductor process cluster tool is performed using a noble gas so as to remove contaminants and reactive gasses at least prior to steps (a) and/or (b). Then, a second heat treatment converts the first composition, including the one or more cobalt silicide phases, into a second silicide composition containing primarily a lower resistivity cobalt silicide phase, the lower resistivity cobalt silicide phase having a resistivity substantially less than the first resistivity.
In a preferred approach, the first heat treatment is performed as an in-situ anneal while the first metal layer is being deposited. Because a small amount of titanium is used in the target the resulting silicide contains trace amounts of the same.
A related aspect of the invention pertains to a method of forming silicide materials in which both sputtering and heat processing operations are performed, to effectuate a type of high temperature sputtering of an alloy layer containing an alloy of Cobalt (Co) and a second refractory metal onto a silicon based substrate. The Co is present in the alloy layer in an amount sufficient for forming a low resistivity salicide contact with the silicon based substrate. While the sputtering is taking place, the silicon based substrate is heated in-situ (by a heating lamp) at a temperature and time sufficient to cause at least partial salicidation of the silicon based substrate and the alloy layer. The final salicidation is achieved during a subsequent heating step, which is at a higher temperature, and which can also be performed in-situ at the same processing station of a cluster chamber.
Yet another aspect of the invention is directed to a method of forming silicide materials on a silicon based substrate using two different layers of cobalt. This process generally include the following steps: (a) depositing a first metal layer on the silicon based substrate, the first metal layer including including an alloy of Cobalt and a refractory metal; and (b) depositing a second metal layer on the silicon based substrate, the second metal layer including a concentration of Cobalt exceeding that of the first metal layer; and (c) performing a first heat treatment substantially contemporaneously with step (b) so as to convert at least part of the first metal layer, the second metal layer and the silicon based substrate into a first silicide composition having one or more cobalt silicide phases, the one or more cobalt silicide phases being characterized by a first resistitivity; and (d) performing a second heat treatment so as to convert the first composition, including the one or more cobalt silicide phases, into a second silicide composition containing primarily a lower resistivity cobalt silicide phase, the lower resistivity cobalt silicide phase having a resistivity substantially less than the first resistivity.
In a preferred approach, the alloy includes about 20 to 80 atomic percent of Ti, and the second metal layer includes a second alloy of Cobalt and a refractory metal. As before, steps (a), (b) and (c) preferably occur within a single semiconductor wafer processing cluster tool.
Yet another aspect of the invention concerns a method of operating a cluster tool to effectuate the aforementioned Co silicide processes and reactions. One representative example uses the following steps: (a) cleaning the silicon based wafer to remove any native oxides and/or contaminants; and (b) out-gassing the silicon based wafer. At this point, the silicon based wafer is substantially water-mark free. Thereafter in step (c) a first metal layer is sputtered on the silicon based wafer using an alloy target comprising cobalt (Go) and at least one refractory metal. Then a step (d) annealing the silicon based wafer in a first anneal treatment to cause the cobalt to react with silicon located on the silicon based wafer is performed. To enhance reliability and productivity, steps (b) through (e) are performed in a single semiconductor wafer processing cluster tool.
Since many cluster tools do not include wet etching, such steps are performed on the silicon based wafer at a processing station separate from the single semiconductor wafer processing cluster tool to remove metals other than silicides. Furthermore, the outgassing step can also occur in a loadlock chamber of the single semiconductor wafer processing cluster tool.
Still another aspect of the invention is directed to a cluster tool for performing semiconductor processing operations on a wafer. The cluster tool is adapted to have: (a) a load lock chamber for receiving the wafer; and (b) a sputter chamber equipped with a cobalt alloy target for sputtering a target material on the wafer; and (c) a heat annealing apparatus for heating the wafer at a rate and temperature sufficient to cause a silicide reaction between the sputtered target material and the wafer.
The load lock chamber is preferably used for outgassing of the wafer. The sputter chamber and the heat annealing apparatus are preferably integrated in a single processing station to effectuate an in-situ, high temperature sputtering operation. A second sputter chamber is also equipped with a second target including cobalt for sputtering a second target material on the wafer. Furthermore, a cleaning station is adapted for performing a cleaning operation on the wafer prior to any sputter operation. Finally, in another variation, a target for the sputter chamber is adjustable in situ so that two different target materials can be deposited on the wafer without changing locations.
Other aspects of the present invention are directed to structures, compositions and semiconductor devices that are formed as a result of the aforementioned Co silicide reactions and processes, and using the cluster tools as described.
These and other aspects of the invention are now described in detail with reference to the attached drawings and other supporting materials provided herein.